Field Effect Transistor technology is a relatively highly developed art, which is currently under extensive development and investigation by the art in general. There are a sizeable number of published articles, patents and text books directed to theory, structure, methods of fabrication, process technology, circuitry and application of field effect devices.
MOSFETs (Metal-Oxide Silicon field effect transistors), MISFETs (Metal Insulator Silicon Field Effect Transistors) and IGFETs (Insulated Gate Field Effect Transistors) are terms extensively employed in the art and possessing well established definitions in the art. "N-channel", "P-channel", "Enhancement Mode", "Depletion Mode" and "CMOS" (Complementary Metal Oxide Silicon) are additional terms extensively employed in the art and possessing well established definitions. At least certain of the foregoing terms will be used hereinafter. When used hereinafter, their use will be in full accord with the generally established definition given said phrase or word in the art.
Numerous texts fully explain the theory of operation of field effect transistors. Two such texts are: (1) "MOSFET in Circuit Design" by Robert H. Crawford (Texas Instrument Series) McGraw Hill, copyright 1967 by Texas Instruments Incorporated and (2) "ELECTRONICS: BJTs, FETs and Microcircuits" by E. James Angelo, Jr., McGraw Hill Electrical and Electronic Engineering Series, copyrighted 1969 by McGraw Hill.
A publication tracing the development of the field effect transistor, evidencing its high state of development, and explaining in non-mathematical terms its operation is the following article: "Metal-Oxide Semiconductor Technology" by William C. Hittinger, Scientific American, August 1973, pages 48 through 57.
U.S. Pat. No. 3,588,848 granted June 28, 1971 to H. W. Van Beek is directed to an Input-Output Control circuit for a complementary MOS integrated memory circuit. The control circuit provides low impedance to bit lines during the "write" cycle and high impedance during the "read" cycle so that the memory cell states won't be changed by control circuit signals.
U.S. Pat. No. 3,644,904 granted Feb. 22, 1972 to L. T. Baker is directed to a chip select circuit for multichip random access memory. The decoding of the chip select signal inhibits the write command signal from all but the selected chip, thereby permitting new data to be written only at the selected chip.
U.S. Pat. No. 3,685,027 granted Aug. 15, 1972 to C. A. Allen is directed to a dynamic MOS memory array chip which utilizes four-device cells. During the refresh cycle, all of the bit/sense line pairs are gated to a charging potential and all of the word lines are pulsed simultaneously so that all cells in the array can be refreshed together. The refresh pulse level applied to all of the word lines is lower than the select pulse level applied to any one of the word lines during a read or write operation.
U.S. Pat. No. 3,706,975 granted Dec. 19, 1972 to R. J. Paluck is directed to a high speed insulated gate field effect transistor random access memory circuit integrated on a monolithic chip. The MOS random access memory circuit utilizes a low voltage decoding circuit that is compatible with transistor-transistor-logic circuit output levels, enabling a reduction in the number of discrete MOS devices required for each memory cell. Also disclosed is a method for decoding wherein all of the lines of the memory matrix are brought high at the start of each cycle, recharging the internal capacitance of all of the memory cells of the matrix. All of the undesired lines of the memory matrix are then discharged through an OR circuit arrangement connected in series with each line, thereby disconnecting all but a preselected cell of the memory matrix from the computer input/output sense lines.
U.S. Pat. No. 3,742,465 granted June 26, 1973 to W. M. Regitz discloses an electronic memory element for use in a random access memory array. The memory element includes three MOS field effect transistors arranged to provide for the binary storage of data. Two additional MOS transistors stabilize the voltages on the bit lines and amplify the read signal. Also disclosed is a sense amplifier, operable during a read cycle, and a digit driver operable during a write cycle.
U.S. Pat. No. 3,745,539 granted July 10, 1973 to E. E. Davidson et al discloses a semiconductor device circuit for reading an FET capacitor store dynamic memory cell and for regenerating the charge (if any) in said capacitor whereby non-destructive read-out is achieved. The memory cell includes an FET switch for selectively connecting the storage capacitor to a memory array bit sense line through either one of a pair of oppositely connected bi-polar transistors for reading and writing, respectively. The bit-sense line is connected to the input terminal of a latching regenerative feedback amplifier such as a silicon controlled rectifier. The potential level at said input terminal rises to a relatively higher level by regenerative feedback action in response to a relatively lower bit sensing voltage which initiates the latching action. The storage capacitor of the memory cell is recharged via one of the bipolar transistors in response to the aforesaid relatively higher potential at the amplifier input terminal. Bipolar current switch embodiments as well as a silicon controlled rectifier embodiment are disclosed for implementing the latching regenerative feedback amplifier.
U.S. Pat. No. 3,761,899 granted Sept. 25, 1973 to V. G. McKenny et al is directed to a dynamic random access memory utilizing MOSFET transistors formed on a single semiconductor chip. The integrated circuit has internal circuits, including storage cells arranged in rows and columns, and interface circuits, including address decoders, etc. for connecting the internal circuits to control circuitry external of the integrated circuit. A primary drain voltage terminal and a primary source voltage terminal are provided for the integrated circuit and are used for the interface circuit. Circuit means formed on the chip establishes a secondary source voltage that is nearer the primary drain voltage than the primary source voltage. The secondary source voltage is used for the internal circuits and reduces loss of data due to injection from the internal circuits.
U.S. Pat. No. 3,795,859 granted Mar. 5, 1974 to J. F. Benante et al is directed to method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors. The electrical characteristics of a field effect transistor of a memory cell connected to a zero bit line and of a field effect transistor of the memory cell connected to a one bit line are determined through applying a substantially constant voltage to one of the zero and one bit lines while changing the voltage condition on the other of the bit lines. Namely, in a memory cell having six FET's with two of the FET's functioning as zero and one active storage devices, two other of the FET's functioning as load devices for the two storage devices, and the final two FET's functioning as switches or controls to connect each of the storage devices to the appropriate bit lines during the read or write operations, it is necessary to determine whether the cell is capable of retaining the data indefinitely.
U.S. Pat. No. 3,795,898 granted Mar. 5, 1974 to R. J. Metha et al, is directed to a random access Read/Write Semiconductor memory for fabrication in integrated circuit form using field effect transistors. It is a dynamic memory having provision for maintaining DC stability in the four transistor memory cells so as to not require periodic refreshing. Buffer and timing circuitry is also provided for minimizing power consumption, for compatibility with TTL circuitry, and for providing read/write access from a single clock signal.
U.S. Pat. No. 3,796,893 granted Mar. 12, 1974 to C. R. Hoffman is directed to circuits for a dynamic MOS RAM having a storage array of inverting storage cells, including an input buffer, a write circuit and a sense circuit. The input buffer circuit includes a dynamic latch circuit clocked by a first clock complement signal and is compatible with TLC logic levels. The cross coupled gate nodes of the dynamic latch are conditionally discharged by circuitry which includes a ratio type first address inverter, and a second ratio type address inverter followed by a third ratioless inverter, whose output conditionally discharges one of the cross coupled gate nodes of the dynamic latch. A separate write circuit drives each digit-sense column bus line, and includes a push-pull driver clocked by a third clock input signal. The pull-up and pull-down field effect transistors of the push-pull driver each have an exclusive OR type circuit for conditionally discharging the precharged gate electrodes of the pull-up and pull-down field effect transistors, depending on the voltages on the data input signal and the data control. The ratioless data control inverter and the data input inverter provide the complement signals required by the two exclusive OR type circuits.
U.S. Pat. No. 3,798,621 granted Mar. 19, 1974 to U. Baitinger et al is directed to a monolithic storage arrangement comprising a plurality of symmetrically disposed bistable storage cells operable as read/write and read-only elements. The storage cell is a modification of a conventional six FET bistable circuit.